This invention is in the field of phase-locked loop circuits, and is more specifically directed to such circuits as used in digital audio systems involving class D output amplification driven by pulse-width-modulated drive signals.
In recent years, digital signal processing techniques have become prevalent in many electronic systems. Tremendous increases in the switching speed of digital circuits have enabled digital signal processing to replace, in large part, analog circuits in many applications. For example, the sampling rates of modern digital signal processing are sufficiently fast that digital techniques have become widely implemented in audio electronic applications.
Digital techniques for audio signal processing now extend to the driving of the audio output amplifiers. A new class of amplifier circuits has now become popular in many audio applications, namely “class D” amplifiers. Class D amplifiers drive a complementary output signal that is digital in nature, with the output voltage swinging fully from “rail-to-rail” at a duty cycle that varies with the audio information. Complementary metal-oxide-semiconductor (CMOS) output drive transistors are thus suitable for class D amplifiers, as such devices are capable of full-rail switching at high frequencies, as desired for digital applications. As known in the art, CMOS drivers are close to ideal switches having very low on-resistance, and their resulting efficiency is especially beneficial in portable and automotive audio applications, as well as in small form factor systems such as flat-panel LCD and plasma televisions, and DVD receivers. The ability to realize the audio output amplifier in CMOS has also enabled integration of an audio output amplifier with other circuitry in the audio system, further improving efficiency and also reducing manufacturing cost of the system. This integration also provides performance benefits resulting from close device matching between the output devices and the upstream circuits, and from reduced signal attenuation.
As is fundamental in the art, several types of audio signals are amplitude-modulated signals, in which a sinusoidal signal (the “carrier”) at a relatively high frequency is amplitude-modulated with the audio information. Conventional tuners include an analog demodulator that mixes the input signal with an unmodulated sinusoid at the carrier frequency in one or more stages, to resolve a difference signal corresponding to the modulated audio information, but at baseband (i.e., audio) frequencies. These conventional tuners then convert the baseband modulation signal to a digital data stream by way of conventional analog-to-digital conversion, at a fixed sample frequency (e.g., 44.1 kHz, or 48 kHz) that is above the Nyquist criterion for the desired audio frequencies. In conventional class D audio systems, the sampled baseband modulation signal is then pulse-width-modulated to produce drive signals for the system speakers.
FIG. 1 illustrates an example of a conventional pulse-width-modulated digital amplifier system. In this system, a digital audio signal, for example a sixteen to thirty-two bit digital datastream AUD_IN, is received by digital audio processing function 3, which performs such conventional functions as parametric speaker equalization or “voicing”, implementation of graphic equalizer presets, treble and bass adjustment, precision soft volume control, loudness compensation, dynamic range compression, background noise floor compensation or noise squelch, center or sub-woofer channel synthesis, programmable dither, peak limiting and clipping, and other digital filter processing. These functions are typically performed by the application of biquad, or second-order IIR, digital filters in a cascade arrangement, as well known in the art. Following such digital audio processing, interpolation function 5 generates an oversampled version of the digital audio signal. Noise shaper and pre-correction filter function 7 then applies conventional digital filter functions to the oversampled signal; as known in the art, noise shaping effectively shifts noise energy away from frequencies of interest (i.e., frequencies that will appear in the audio band), and into portions of the bandwidth that have no effect on the output audio signal. The output of functions 3, 5, 7 is pulse-code-modulated (PCM) signal PCM_SIG that is applied to PCM to PWM conversion function 9, which in turn converts PCM signal PCM_SIG into pulse-width-modulated (PWM) output signal PWM_SIG. Signal PWM_SIG drives power stage 8, which in this example is a conventional class D power amplifier. which drives speaker SPKR. Class D power stage 8, in this example, drives speaker SPKR, via its apparent LC filter 11, in either full-bridge or half-bridge fashion, depending on the system design.
For purposes of this description, the frequency of signal PCM_SIG as output by function 7 is based on sampling frequency fs, which is the frequency of the incoming digital audio signal AUD_IN (or a sampling frequency to which signal AUD_IN is converted by sample rate conversion, such as in a system that can receive various audio input sources). Signal PCM_SIG thus has a frequency at a multiple of sampling frequency fs, with the multiple determined by the oversampling rate of interpolation function 5. For example, a typical sampling frequency fs for digital audio is 48 kHz, and a typical oversampling multiple is eight, resulting in a frequency of 8fs=384 kHz for the signal PCM_SIG as applied to PCM to PWM conversion function 9. Signal PCM_SIG is typically a multiple-bit signal (e.g., eight bits) for each audio channel (one of which is illustrated in FIG. 1).
PCM to PWM conversion function 9, as mentioned above, converts the PCM signal PCM_SIG to a PWM signal PWM_SIG. The frequency of signal PWM_SIG is based upon a clock signal PWM_CLK, which in this example is generated by phase-locked loop (PLL) 6. PLL 6 is a conventional analog phase-locked loop, which generates its output clock signal PWM_CLK at a phase and frequency relationship relative to a clock signal at its input. This clock PWM_CLK is a very high frequency clock, as its period defines the pulse width of the smallest PWM pulse generated by PCM to PWM function. For example, if signal PCM_SIG is an eight-bit signal at a frequency of 8fs that that is to be converted into a double-sided symmetrical PWM duty cycle value, the frequency of PWM clock PWM_CLK ought to be 512 times 8fs; for a sampling frequency fs of 48 kHz, therefore, the frequency of clock PWM_CLK would be about 196 MHz. While “single-sided” PWM would require a PWM clock of only 256 times 8fs, a doubled clock frequency is preferable, to maintain symmetry of the PWM signal, as known in the art. In this conventional system of FIG. 1, the reference clock signal is based on master clock signal MSTR_CLK, which is received from external to the digital audio system and which is applied to PLL 6, after the appropriate frequency division by frequency divider 4 to the extent desired by the designer.
A typical power spectral density (PSD) spectrum for the output PWM signal PWM_SIG is illustrated in FIG. 2. Spike 12 indicates the output audio signal carried by the PWM output signal, for example at about 20 kHz and thus within the audio band. Spike 14 represents the power at the switching frequency 8fs=384 kHz, in this example, with carrier sidebands 16 disposed on either side of this fundamental. As evident from FIG. 2, the signal power of signal PWM_SIG is concentrated at harmonics of the switching carrier, with spikes at odd-numbered harmonics of the switching frequency 8fs=384 kHz (e.g., spike 19 at the third harmonic, at 1152 kHz), but with spikes from the carrier sidebands centered also around even harmonics of the switching carrier. FIG. 2 also illustrates the effects of noise shaping function 7, which moves or concentrates noise energy at frequencies between the fundamental and harmonics of the switching frequency 8fs=384 kHz. This noise shaping helps to reduce the noise energy at those frequencies at which the PWM output signal provides significant energy.
As mentioned above, the frequency of signal PWM_SIG is generated by PLL 6, based on a reference clock signal that is, in turn, based on an external master clock signal MSTR_CLK. This master clock signal MSTR_CLK is typically slaved to the input signal source, and based on an external crystal reference. It has been discovered, in connection with this invention, that the frequency of this master clock signal MSTR_CLK is therefore generally not sufficiently stable for high-fidelity digital audio systems. Indeed, it has been discovered, in connection with this invention, that the actual noise in the audio band is generally dominated by phase jitter in the PWM clock signal PWM_CLK, which is of course directly dependent on the phase jitter in the master clock signal MSTR_CLK. FIG. 3 qualitatively illustrates the noise energy resulting from phase jitter in the master clock signal. Curve 15 illustrates the noise energy from master clock phase jitter upon the fundamental of the switching frequency (e.g., at 384 kHz), while curve 17 illustrates the noise energy from this jitter upon the third harmonic of the switching frequency (i.e., centered at 1152 kHz in this example). As evident from FIG. 3, the noise energy from the fundamental and odd harmonics of the PWM switching frequency extends into the audible frequency band (e.g., around 20 kHz).
But master clock signal MSTR_CLK is typically generated using fractional synthesis from a 27 MHz crystal reference, and as such has wide-band phase noise, with multiple spurs. While a crystal-based master clock signal will itself not have significant phase jitter, it has been observed that jitter is still present due to the fractional synthesis circuitry for generating master clock signal MSTR_CLK from the 27 MHz crystal reference. Characterization of typical clock signals generated in this fashion shows that on the order of 20 dB of dynamic range in the digital audio system is lost due to typical phase jitter in this master clock signal, especially considering that this master clock signal MSTR_CLK is further frequency multiplied by a factor of sixteen or so in the generation of the high speed PWM clock. Conversely, 30 dB or more of jitter attenuation is required in the phase-locked loop, in order to produce a PWM clock signal with sufficiently low noise energy as to safely attain the desired level of 100 dB audio performance in an actual implementation.
Using conventional approaches, such a high degree of jitter attenuation typically requires a low closed-loop frequency in the phase-locked loop used to generate the PWM clock signal. And, as known in the art, low closed-loop frequency operation of a PLL generally requires a voltage-controlled oscillator and a loop filter that each have extremely low intrinsic noise. Analog implementation of such a PLL necessitates large passive components, which therefore must be external to the audio processor integrated circuit. These external components are not only costly to the system manufacturer, but also add to the cost of the integrated circuit realizing the PLL, by requiring additional integrated circuit chip and package space for connections to the external components.
As known in the art, the digital implementation of phase locked-loop circuits is attractive for many reasons. The cost and inefficiency resulting from external passive filter components makes a digital PLL implementation attractive. As noted above, the elimination of off-chip loop filter components to obtain performance on a par with low closed-loop frequency PLLs, is necessary in generating a high frequency clock signal from a relatively “sloppy” reference clock. Other benefits of digital PLL realizations include improved speed of design and design verification of the circuits, scalability and portability of digital designs to other applications and new manufacturing processes, reduced noise sensitivity due to operation in the digital domain, and reduced cost of manufacture because of the elimination of large analog circuits such as band-gap reference circuits and charge pumps.
By way of further background, conventional digital PLL circuits have been analyzed, in connection with the invention. In at least one example of a conventional application specific integrated circuit (ASIC) cell available from Texas Instruments Incorporated, the spectrum of phase noise showed notches at 8 MHz offsets from the center frequency, for such a PLL operating in response to an 8 MHz reference clock signal.